Most computers and other digital systems have a system memory which often consists of dynamic random access memory (“DRAM”) devices. DRAM devices are fairly inexpensive because a DRAM memory cell needs relatively few components to store a data bit as compared with other types of memory cells. Thus, a large system memory can be implemented using DRAM devices for a relatively low cost. However, DRAM devices have the disadvantage that their memory cells must be continually refreshed because of the inherently transitory nature of their storage technology.
Generally a DRAM memory cell consists of a transistor/capacitor pair. High and low voltages stored in the capacitor represent logical one and zero data bits, respectively. In a basic DRAM memory cell, one plate of the capacitor is connected to the drain of the transistor, and the other plate is connected to ground. A data bit is written to the cell by enabling the gate of the transistor and applying a voltage corresponding to the data bit to be written to the transistor's source. The enabled transistor conducts the voltage to the capacitor, charging the capacitor and storing the data bit. When the transistor is disabled, the data bit remains stored. Re-enabling the transistor reconnects the capacitor to the source of the transistor, and the stored voltage representing the data bit can be read at the source.
The foregoing is a simplified view, ignoring two considerations presented by the physical nature of the capacitor used in the memory cell. First, a capacitor can hold a voltage only briefly. The smaller the capacitor, the shorter is the duration for which the voltage can be stored. In a DRAM memory device containing thousands of memory cells on a single piece of a semiconductor wafer, these capacitors are infinitesimal, and can only reliably maintain a voltage for microseconds. Consequently, these memory cells must be refreshed thousands of times per second. Second, because these stored voltages dissipate so rapidly, reading the voltage after just a short interval requires a sense amplifier. The use of a sense amplifier is well known in the art to detect whether a stored voltage is high or low, and drive it toward the appropriate binary voltage parameter of the digital device. Fortunately, reading each cell using a sense amplifier not only reads the bit stored in the cell, but also simultaneously refreshes the voltage stored in that cell. The use of sense amplifiers to read and refresh DRAM memory cells is well known in the art. In the interest of brevity, the details of their operation will not be recounted here.
Constantly refreshing DRAM memory cells presents two problems. First, refreshing memory cells slows the useful function of the memory. Memory cells are presented in arrays of rows and columns, often thousands of rows deep and thousands of columns wide. Even though entire rows of an array are refreshed at a time, it still requires thousands of refresh operations to refresh every row in the array. Moreover, these memory arrays cannot be accessed during a refresh cycle. Unless the memory array is equipped with a dual accessing mechanism, a row cache device, or similar means, the array can be neither read from nor written to during a refresh cycle without interrupting or destroying the cycle. If the central processing unit or other controller initiates a memory read or write operation during a refresh cycle, the processor or controller will have to wait for completion of that refresh cycle. This waiting slows processing throughput.
Second, and even more problematic than processing delays, is the power consumed in the continual, rapid refreshing of these memory cells. Thousands of times per second, the gate of each transistor in each memory cell across the entire DRAM array must be activated to refresh the array. Resistance of the conductors through the memory array to address each and every transistor, in each and every row, in each and every column, consumes considerable power. More power is consumed by transistors used in the sense amplifiers which read and refresh the memory cells in respective columns. Still further, supporting circuitry needed to access the rows of memory cells, such as a refresh counter, row multiplexers, row decoders, and address latches, uses even more power.
A simplified view of a typical, conventional DRAM memory array is depicted in FIGS. 1 and 1A. Both show part of a 256 Mb array 110 which stores data in two conventional DRAM memory banks 112 and 114. Each memory bank 112 and 114, for example, has 8,192 rows of memory cells, for a total of 16,384 rows. The figures are simplified most notably in the sense that they omit components such as column address multiplexers, column address latches, and column decoders. As is well known, reading from or writing to a memory bank requires both a row and a column address to identify the specific memory location where the data is or will be stored. Both row and column addressing circuits are needed to read from and write data to the memory banks. On the other hand, refreshing a memory bank is typically performed by reading and thereby refreshing an entire row at a time across each memory bank, and column addresses are irrelevant. The invention described in this application is directed to a system and method for refreshing a memory array, thus column addressing is not germane. Further discussion of column addressing means has been omitted for the sake of simplicity.
A memory array can be refreshed in either a burst refresh mode or a distributed refresh mode. Using a burst refresh mode, every row of a memory array is sequentially refreshed in rapid succession. Then, after every passage of a predetermined interval, every row of the memory array again is refreshed in rapid succession. The maximum duration of the predetermined interval is the span of time after which the data stored in the DRAM array begins to degrade less the time required to sequentially refresh every row in the array. This standard interval is necessarily brief considering the rapid refreshing needs of a conventional DRAM device.
FIG. 1 depicts a system memory which employs burst refresh. A refresh controller 120 generates a refresh signal after the passage of the predetermined interval. Incremented by each pulse of a refresh clock 122, a refresh counter 124 sequences through a series of 14-bit binary numbers. The 14-bit binary number equates to one of 214 or 16,384 numbers, one of which uniquely corresponds to the address of each row of one of the two memory banks 112 and 114.
Each row in the memory banks 112 and 114 is accessed through a network of addressing circuitry 160 which includes a row address multiplexer 130, row address latch A 150, row address latch B 152, and row decoders 132-142. Depending upon whether the row address generated by the refresh counter 124 refers to a row in memory bank A 112 or memory bank B 114, the row address is directed by the row multiplexer 130 to row address latch A 150 or row address latch B 152, respectively. From the appropriate row address latch 150 or 152, five bits of the 14-bit address uniquely identify one of the 25 or sixteen row decoders 132-142 associated with each memory bank. The remaining nine bits of the address uniquely correspond to one of the 29 or 512 rows addressed by each row decoder 132-142. Only a few of the sixteen row decoders needed for each memory bank 112 and 114 are shown in the figures for the sake of visual clarity.
After supplying the address of a row to the appropriate memory bank 112 or 114, that row will be read and thereby refreshed by sense amplifiers incorporated in each memory bank 112 and 114. In this manner, the entire memory array is refreshed, row by row. Once the refresh counter 124 has sequenced through all 16,384 row addresses, the refresh cycle is over. The refresh counter 124 and the addressing circuitry 160 sit idle, consuming power, awaiting the next refresh signal from the refresh controller 120 or the next external address signal 126.
Using a distributed refresh mode, one row of the memory array is refreshed, then, after passage of a predetermined interval, the next row of the array is refreshed. This process is repeated until every row in the memory array is refreshed. The predetermined interval between the refreshing of each row is far shorter than the predetermined interval between refresh cycles in a burst refresh context. The maximum duration of the predetermined interval between row refreshes is the span of time after which the data stored in the DRAM array begins to degrade, less the time required to sequentially refresh every row in the array, divided by the number of rows in the array. In other words, all other variables being equal, the predetermined interval in the distributed refresh mode would be equal to the predetermined interval in the burst refresh mode divided by the number of rows in the memory array. For example, assuming that the span of time after which the data stored in the DRAM array begins to degrade and the total time to refresh the rows themselves is equal to that for the DRAM array refreshed in a burst refresh mode, and there are 8,192 rows in the array, the predetermined interval between row refreshes in a distributed refresh would be 1/8,192 as long as the predetermined interval between array refreshes in a burst refresh.
FIG. 1A depicts a system memory which employs distributed refresh. The refresh cycle in a distributed refresh mode is largely similar to the refresh cycle in a burst refresh mode, as reflected by how similar FIG. 1A is to FIG. 1. The essential difference in a memory system employing distributed refresh is that there is not a single signal from the refresh controller 120 which initiates a refresh of the entire memory array. Instead, after each passage of the much shortened predetermined interval, the refresh controller 120 generates a refresh signal that causes one row of either memory bank A 112 or memory bank B 114 to be refreshed. The refresh controller 120, instead of enabling a rapid count of the refresh counter 124 through its entire sequence, pulses the refresh counter 124 causing its count to be incremented by one. This row address is passed to the addressing circuitry 160 which reads and thereby refreshes one row of the array in an identical manner as to how each row of the memory array is refreshed in a burst refresh. Then, after the passage of another much shortened predetermined interval, the refresh controller 120 emits another refresh signal which increments the refresh counter 124, which, in turn, causes the next row in the memory array to be read and refreshed. This process repeats continually.
Regardless of which mode of refresh is employed, merely the number of devices needed to refresh the array suggests that significant power is consumed in refreshing the array. Moreover, in an actual system memory, power would have to be supplied to eight times as many memory cells and decoders for every byte of data stored. For example, to store 256 MB of data, eight parallel 256 Mb arrays are needed, each of which has its own two banks of memory cells, sixteen row decoders, two row address latches, and a row address multiplexer. The aggregate amount of power used to refresh the cells throughout an entire system memory becomes relatively immense.
The power expended in these refresh cycles is a significant problem. Most significantly, excessive power consumption quickly exhausts battery power in increasingly popular portable computing devices. The consumption of this power also generates a great deal of heat. For all the power expended in refreshing these DRAM memory cells, an additional—and substantial—quantity of power is expended by cooling fans in eliminating the waste heat produced during these refresh cycles.
Much of the power wasted in refreshing DRAM memory could be saved by using less volatile DRAM devices. Instead of having to be refreshed thousands of times per second, after the passage of only a brief interval, less volatile DRAM devices only need to be refreshed after the passage of an extended interval. For one example, programmable conductor dynamic random access memory (PCDRAM) devices need to be refreshed far less frequently than conventional DRAM devices. One known form of PCDRAM memory cell 200, as depicted in FIG. 2A, uses a conducting layer 202, which may be comprised of silver, applied to an insulating layer 204, which may be comprised of glass. The conducting layer 202 and insulating layer 204 are perpendicularly disposed in a frame of insulating material 206. Conducting plates 208 and 210 are disposed on outermost surfaces of the conducting layer 202 and insulating layer 204, respectively. Tautologically, the conducting layer 202 conducts, whereas the insulating layer 204 does not conduct. When a low voltage is applied across the conducting plates 208 and 210, the voltage will not be conducted because it will be blocked by the insulating layer 204. Therefore, the memory cell is 200 not conductive in its initial state.
However, applying a relatively high voltage across the conducting plates 208 and 210 causes the cell to become conductive by changing the structure of the cell 200. FIG. 2B depicts the same memory cell 200 after a relatively high voltage has been applied. The relatively high positive voltage forces dendrils 212 of the material from the conducting layer 202 through the insulating layer 204 toward the conducting plate 210 disposed on the insulating layer 204. Formation of the dendrils 212 of material from the conducting layer 202 through the insulating layer 204 is caused by the charged metal particles being attracted and repelled by fields of differing or similar charge, respectively. This phenomenon is known, and will not be described further here in the interest of brevity.
Because the voltage has driven dendrils 212 of material from the conducting layer 202 through the insulating layer 204 to contact the conducting plate 210 on the opposite surface of the insulating layer 204, the cell 200 becomes conductive. The cell 200 will now conduct when even low voltages are applied, thus, this cell effectively now stores a logical one which later can be read by the system associated with the memory cell 200.
The memory cell 200 can also be reprogrammed to store a logical zero. As shown in FIG. 2C, after application of a relatively high voltage of reverse polarity, i.e., with the positive voltage applied to the conducting plate 210, reverses the migration of the dendrils 212 of material from the conducting layer. The dendrils 212 of material from the conducting layer 202 passing through the insulating layer 204 are forced back toward the conducting layer 202 and out of the insulating layer 204 by the same natural attraction and repulsion of charges which originally caused the cell to be programmed. This relatively high voltage of reverse polarity causes the memory cell 200 to become nonconductive once more. When a lesser voltage is applied, the memory cell 200 will no longer conduct. Thus, and the cell now effectively stores a logical zero. In sum, higher voltages of opposite sense can be used to program and reprogram these cells to conduct or not conduct, storing logical ones or zeroes, respectively.
The PCDRAM memory cell 200 described is far less volatile than a conventional DRAM memory cell. Without being refreshed, a conventional DRAM cell only can maintain its logical bit for microseconds, while the PCDRAM memory cell 200 potentially can maintain its logical bit for days. Eventually, natural diffusion of the material from the conducting layer 202 into and out of the insulating layer 204 resulting from ordinary atomic motion will corrupt the data stored. Nonetheless, PCDRAM devices need only be refreshed after an extended interval, thus, less power is needed to refresh these devices than is needed for the frequent refreshing required by conventional DRAM devices.
The problem remains that systems designed to work with conventional DRAM arrays are very common and standardized. One might substitute an array of PCDRAM memory cells in place of an array of conventional DRAM cells. However, power still would be wasted because control systems designed to work with conventional DRAM cells would refresh the PCDRAM cells at a rate consistent with the refresh rate requirements of conventional DRAM cells. The PCDRAM memory cells would be refreshed at a rate that is significantly higher than is required, wasting power.
The need to redesign circuitry interfacing with the DRAM devices to take advantage of the power savings possible with PCDRAM devices may, at least initially, limit the usefulness of and market demand for PCDRAM devices. What is needed is a way to allow circuitry developed to refresh conventional DRAMs to work with PCDRAMs without wasting power. It is to this need that the present invention is directed.